GE Plugs into Industrial Internet
pMTJ Is Where the MRAM Action Is
Allied with Intel, CEA-Leti Shoots for Moon
Baidu Releases AI Benchmark
Chip Market to Go Down, says Future Horizons
Excellicon Tools Used by Renesas to Streamline Timing Constraint Development Methodology
Cadence Announces General Availability of Tensilica Xtensa LX7 Processor Architecture, Increasing Floating-Point Scalability with 2 to 64 FLOPS/Cycle
MoSys Announces Oricane Support of Custom Algorithm Development for Its Programmable Search Engine to Accelerate Cloud Infrastructure, Security, and Processing Solutions
Dr. Andrzej J. Strojwas of Carnegie Mellon University Honored With 2016 Phil Kaufman Award
TSMC Recognizes Synopsys with Three Partner Awards for Interface IP and Joint Development of 7-nm Mobile and HPC Design Platforms
EdXact News (detailed articles open at bottom)
Silvaco Group Acquires edXact for SPICE Simulation Speed-up
EdXact Silver Sponsor at CDNLIVE Silicon Valley 2016
EdXact Releases Version 5.6 of Jivaro-A
EdXact Exhibits at CDNLive Boston 2015
It's DAC time!
EdXact at CDN Live EMEA 2015!
EdXact Participates at SNUG 2015 Designer Community Expo
EdXact Participates at CDNLIVE Silicon Valley 2015
EdXact Exhibits at Synopsys SIG Meeting, hosted at DesignCon
EdXact delivers version 1.9 of Alps, Viso, Belledonne
Meet us ...
Cadence Live Silicon Valley - April 5 2016 [Santa Clara, USA]
Cadence Live User Group Meeting - May 2-4 2016 [Munich, Germany]
IEEE Workshop on Signal and Power Integrity - May 8-11 2016 [Turin, Italy]
Design Automation Conference - June 5-9 2016 [Austin, USA]
TSMC OIP Ecosystem Forum - June 13 2016 [Amsterdam, Netherlands]
Grand Technology Seminar - July 2016 [Hsinchu, Taiwan]
Cadence Live Boston - August 31 2016 [Boston, USA]
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