Integre Brings x1 HyperLink DSP to FPGA
March 28 is Arduino Day -- Break Out the Party Hats!
SanDisk Goes For Big Data Flash Market
Four Steps to Field-Oriented Control -- The Final Two
Teensy-Weensy GPAK4 Mixed Signal FPGAs
Intel to buy Altera (Wall Stree Journal)
Video: Interview Mike Bartley, CEO of TVS - Test and Verification at 2015 DVCon.
Wolfram's new SystemModeler version brings new capabilities
"Taking Control of Constraints Verification" by Sarath Kirihennedige
S2C technical paper: FPGA Prototyping of System-on-Chip Designs
EdXact News (detailed articles open at bottom)
EdXact Participates at SNUG 2015 Designer Community Expo
EdXact Participates at CDNLIVE Silicon Valley 2015
EdXact Exhibits at Synopsys SIG Meeting, hosted at DesignCon
EdXact delivers version 1.9 of Alps, Viso, Belledonne
EdXact delivers new versions of Alps, Viso, Belledonne and Brenner
Version 5.5 of Jivaro is getting delivered
EdXact demonstrates Unique Capabilities for FinFet and TriGate Support at DAC
EdXact and Oasic to present flow prototype at edaWorkshop14 in Hanover, Germany
Version 1.7 of Belledonne is ready!
EdXact Releases Version 5.4 of Jivaro-D
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Synopsys SNUG Silicon Valley - March 23-25 2015 [Santa Clara, USA]
Cadence Live User Group Meeting - April 27-28 2015 [Munich, Germany]
Design Automation Conference - June 7-11 2015 [San Francisco, USA]
Grand Technology Seminar - July 2015 [Hsinchu, Taiwan]
Cadence Live Boston - September 2 2015 [Boston, USA]
Synopsys HSPICE SIG at DesignCon - Jan 28 2015 [Santa Clara, USA]
Cadence Live Silicon Valley - March 10-11 2015 [Santa Clara, USA]
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